1. Field of the Invention
The present invention relates generally to a multi-gate MOSFET and a process thereof, and more specifically to a multi-gate MOSFET and a process thereof, which forms a liner on the sidewalls of a part of the fin-shaped structure, and then oxidizes apart of the fin-shaped structure not covered by the liner and a part of a substrate between each of the fin-shaped structures.
2. Description of the Prior Art
With increasing miniaturization of semiconductor devices, various multi-gate MOSFET devices have been developed. The multi-gate MOSFET is advantageous for the following reasons. First, manufacturing processes of multi-gate MOSFET devices can be integrated into traditional logic device processes, and are therefore more compatible. In addition, since the three-dimensional structure of the multi-gate MOSFET increases the overlapping area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effects and short channel effects. Moreover, the channel region is longer for a similar gate length. This way, the current between the source and the drain is increased.
In the present semiconductor process, a localized oxidation isolation (LOCOS) or a shallow trench isolation (STI) is normally used to isolate each MOS. However, due to the reduction in both design sizes and fabricating line widths of the semiconductor wafers, pits, crystal defects and longer bird's beak in the LOCOS process will greatly affect the characteristics of the semiconductor wafer. In the same way, the field oxide produced in the LOCOS process occupies a larger volume, which affects the integration of the semiconductor wafer. Thus, in the submicron semiconductor processes, the STI process is widely used as an isolation technique, thanks to its smaller size and improved integration, to isolate each of the multi-gate MOSFET components, especially by forming shallow trench isolation structures between each of fin-shaped structures to electrically isolate them from each other.
Moreover, in nowadays multi-gate MOSFET processes, ion implantation processes and annealing processes may be performed below each fin-shaped structure and the substrate between each of the fin-shaped structures, so as to form channel stop layers with an opposite electrical type below them, in order to electrically isolate transistors formed on each fin-shaped structure. However, the dopants imported during the ion implantation processes are not enough, leading to circuit leakage caused by each of the fin-shaped structures being electrically incompletely isolated.